NOVEL FLIPFLOP DESIGN USING GDI TECHNIQUE

Abstract

Low power, low space, and high-speed design of flip flops using fewer transistors are discussed in this
study. When designing digital circuits, the Modified Gate Diffusion Technique (M-GDI) is an alternative
to CMOS and PTL (Pass Transistor Logic). As a result, the size of the circuit and the amount of power
dissipation are both reduced. A thorough evaluation of existing designs of True SinglePhase Clocking
Flip-Flops with positive edge triggers is performed. Minimize transistor size and power dissipation as
compared to the design of real single-phase clocking flip-flop (FF) transistors in this study Master-slave
logic is used in the design.