Equal Segmentation based Approximate Adder Design for High Speed Operations

Abstract

It's not always necessary to get the most accurate results in many cases, such as in image and
multimedia data processing, artificial intelligence, and machine learning. As a result, approximation
computing has been developed. Using approximation computing makes a big impact in terms of the
amount of space, latency, and power used. It may not be the best choice for error-resistant applications
since its ED is too high; and Error also rises as bandwidth increases. This research introduced a novel
strategy that is equally segmented in order to enhance these parameters. Using this technique, an N-bit
adder is broken down into equal-sized and accurate sub-adders. Segment size (k) is one of two factors
used to build an N-bit ESA. Carry propagation length and Overlapping bits are two examples of this. It's
the bare minimum in terms of carry prediction bits. So the best configurations differ depending on the
ESA adder design. Three kinds of adder architectures are included in our analysis: those with smaller
area; those with smaller delay; and those with an in-between delay and area size.