Design and Analysis of Low Power, High Performance 2-4and4- 16Mixed-Logic Line Decoders

Abstract

Line decoders are being designed using a mixed-logic approach that incorporates transmission gate
logic, dual-value logic using pass transistors, and static CMOS. The 2-4 decoders are given with two new
topologies. 14-transistor and 15-transistor topologies attempting to minimize transistor count and
power dissipation, respectively. A normal and an inverted decoder is used in each situation to create a
total of four unique designs. Four novel decoders for the 4-16 range have been built, using mixed-logic
2-4 pre-decoders and a regular CMOS post-decoder. As opposed to their typical CMOS counterparts, all
of the proposed decoders feature full swinging functionality and a significantly decreased transistor
count. At the 32nm node, the suggested circuits offer significant improvements in power and latency
over CMOS in almost all circumstances, according to a range of comparative computer simulations.